-------------------------------------------------------------------------------
-- FILE: components_pack.vhd
-- DESCRIPTION: This package declares the components to be used throughout the
-- design process. Add more components if needed.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

package components_pack is

	-- D-flipflop
	component dff
		generic(
			w : integer);
		port(
			clk, rst : in  std_logic;
			d        : in  std_logic_vector(w - 1 downto 0);
			q        : out std_logic_vector(w - 1 downto 0));
	end component;

	-- Addition unit
	component adder
		generic(
			w1 : integer;
			w2 : integer);
		port(
			in1    : in  std_logic_vector(w1 - 1 downto 0);
			in2    : in  std_logic_vector(w2 - 1 downto 0);
			output : out std_logic_vector(w1 - 1 downto 0));
	end component;

	-- Combinatorial fixed multiplication unit
	component fixed_mult_comb
		generic(
			w            : integer;
			w_m          : integer;
			multiplicand : integer);
		port(
			input  : in  std_logic_vector(w - 1 downto 0);
			output : out std_logic_vector(w + w_m - 1 downto 0));
	end component;

end components_pack;

------------------------------------------------------------------------------
-- component dff
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity dff is
	generic(
		w : integer);

	port(
		clk, rst : in  std_logic;
		d        : in  std_logic_vector(w - 1 downto 0);
		q        : out std_logic_vector(w - 1 downto 0));

end dff;

architecture behavioral of dff is
begin                                   -- behavioral

	process(clk)
	begin
		if (clk'event and clk = '1') then
			if (rst = '0') then
				q <= (others => '0');
			else
				q <= d;
			end if;
		end if;
	end process;

end behavioral;

-------------------------------------------------------------------------------
-- component adder
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;

entity adder is
	generic(
		w1 : integer;
		w2 : integer);

	port(
		in1    : in  std_logic_vector(w1 - 1 downto 0);
		in2    : in  std_logic_vector(w2 - 1 downto 0);
		output : out std_logic_vector(w1 - 1 downto 0));

end adder;

architecture behavioral of adder is

-- YOUR CODE
begin
	--	output <= (In1(w1 - 1) & In1) + In2;
	output <= In1 + In2;

end behavioral;

-------------------------------------------------------------------------------
-- component combinatorial fixed_mult
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;

entity fixed_mult_comb is
	generic(
		w            : integer;
		w_m          : integer;
		multiplicand : integer);

	port(
		input  : in  std_logic_vector(w - 1 downto 0);
		output : out std_logic_vector(w + w_m - 1 downto 0));
--		output : out std_logic_vector(w - 1 downto 0));

end fixed_mult_comb;

architecture behavioral of fixed_mult_comb is
begin                                   -- behavioral

	output <= input * conv_std_logic_vector(multiplicand, w_m);

end behavioral;
